Intel leans hard on advanced chip packaging technologies in battle for computing supremacy

This newsletter is a part of the Era Perception sequence, made conceivable with investment from Intel.

We generally tend to concentrate on the newest and biggest era nodes as a result of they’re used to fabricate the densest, quickest, maximum power-efficient processors. However as we have been reminded all through Intel’s contemporary Structure Day 2020, a spread of transistor designs is had to construct heterogeneous techniques.

“No unmarried transistor is perfect throughout all design issues,” mentioned leader architect Raja Koduri. “The transistor we’d like for a functionality desktop CPU, to hit super-high frequencies, may be very other from the transistor we’d like for high-performance built-in GPUs.”

Right here’s the issue: collecting processing cores, fixed-function accelerators, graphics assets, and I/O, after which etching all of them onto a monolithic die at 10nm makes production very, very, tricky. However the choice—breaking them aside and linking the items—gifts demanding situations of its personal. Inventions in packaging conquer those hurdles by way of making improvements to the interface between dense circuits and the forums they populate.

Advanced packaging is all about mixing and matching the right transistors for each application to speed time to market while maximizing performance.

Above: Complicated packaging is all about mix and matching the appropriate transistors for every software to hurry time to marketplace whilst maximizing functionality.

Again in 2018, Intel laid out a plan to get smaller gadgets operating in combination with out sacrificing velocity. “We mentioned that we wish to expand era to glue chips and chiplets in a equipment that may fit the functionality, chronic potency, and value of a monolithic SoC,” persisted Koduri. “We additionally mentioned we’d like a high-density interconnect roadmap that allows excessive bandwidth at low chronic.”

In an trade keen to call winners and losers according to procedure era, leading edge approaches to packaging might be power multipliers within the combat for computing supremacy. Let’s have a look at Intel’s present packaging playbook, along side the teasers disclosed all through its contemporary Structure Day 2020.

KEY POINTS:

  • The Embedded Multi-die Interconnect Bridge (EMIB) facilitates die-to-die connections the usage of tiny silicon bridges embedded within the equipment substrate
  • The Complicated Interface Bus (AIB) is an open-source interconnect usual for developing high-bandwidth/low-power connections between chiplets
  • Foveros takes packaging to the 3rd size with stacked dies. The primary Foveros-based product will goal the distance between laptops and smartphones.
  • Co-EMIB and the Omni-Directional Interface promise scaling past Intel’s current packaging applied sciences by way of facilitating higher flexibility.

Overcoming monolithic rising pains with EMIB

Till lately, in the event you sought after to get heterogeneous dies onto a unmarried equipment for optimum functionality, you positioned the ones dies on a work of silicon referred to as an interposer and ran wires during the interposer for verbal exchange. Via silicon vias (TSVs) — electric connections — handed during the interposer and right into a substrate, which shaped the equipment’s base.

The trade refers to this as 2.5D packaging. TSMC used it to fabricate NVIDIA’s Tesla P100 accelerator again in 2016. A 12 months prior to that, AMD mixed a large GPU and 4GB of high-bandwidth reminiscence (HBM) on a silicon interposer to create the Radeon R9 Fury X. Obviously, the era works. However it provides an inherent layer of complexity, slicing into yields and including vital value.

Intel’s Embedded Multi-die Interconnect Bridge (EMIB) goals to mitigate the restrictions of two.5D packaging by way of ditching the interposer in prefer of tiny silicon bridges embedded within the substrate layer. The bridges are loaded with micro-bumps that facilitate die-to-die connections.

“The present technology of EMIB provides a 55 micron micro-bump pitch with a roadmap to get to 36 microns,” mentioned Ramune Nagisetty, director of procedure and product integration at Intel. Examine that to the 100-micron bump pitch of a normal natural equipment. EMIB makes it conceivable to succeed in a lot upper bump density because of this.

Small silicon bridges also are so much more economical than interposers. While the Tesla P100 and Radeon R9 Fury X have been high-dollar flagships, one in every of Intel’s first merchandise with embedded bridges was once Kaby Lake G, a cell platform that mixed eighth-gen Core CPUs and AMD Radeon RX Vega M graphics. Laptops according to Kaby Lake G weren’t reasonable by way of any measure. However they demonstrated EMIB’s talent to get heterogeneous dies onto one equipment, consolidating treasured board area, augmenting functionality, and riding down value in comparison to discrete elements.

In this example, EMIB creates a high-density connection between the Stratix 10 FPGA and two transceiver dies.

Above: On this instance, EMIB creates a high-density connection between the Stratix 10 FPGA and two transceiver dies.

Intel’s Stratix 10 FPGAs additionally make use of EMIB to glue I/O chiplets and HBM from 3 other foundries, manufactured the usage of six other era nodes, on one equipment. Through decoupling transceivers, I/O, and reminiscence from the core cloth, Intel can select and make a selection the transistor design for every die. Including strengthen for CXL, sooner transceivers, or Ethernet is as simple as swapping out the ones modular tiles attached by way of EMIB.

Standardizing die to die integration with the Complicated Interface Bus

Earlier than chiplets will also be combined and paired, the reusable IP blocks should understand how to speak to one another over a standardized interface. For its Stratix 10 FPGAs, Intel’s embedded bridges raise the Complicated Interface Bus (AIB) between its core cloth and every tile.

AIB was once designed to allow modular integration on a equipment in a lot the similar means PCI Categorical facilitates integration on a motherboard. However while PCIe drives very excessive speeds via few wires, AIB exploits the density of EMIB to create a large parallel interface that operates at decrease clock charges, simplifying the circuitry to transmit and obtain whilst nonetheless attaining very low latency.

Reusable IP blocks on a package may be connected by silicon bridges or interposers using the Advanced Interface Bus to move data over a wide parallel connection.

Above: Reusable IP blocks on a equipment is also attached by way of silicon bridges or interposers the usage of the Complicated Interface Bus to transport knowledge over a large parallel connection.

The primary technology of AIB provides 2 Gb/s cord signaling, enabling Intel’s imaginative and prescient of heterogeneous integration with monolithic SoC-like functionality. A second-generation model, anticipated to tape out in 2021, helps as much as 6.four Gb/s in step with cord, bump pitches as tight as 36 microns, decrease chronic in step with bit transferred, and backward compatibility with current AIB implementations.

It’s value noting that AIB is packaging agnostic. Despite the fact that Intel connects its tiles the usage of EMIB, TSMC’s Chip-on-Wafer-on-Substrate (CoWoS) era may just raise AIB, too.

Previous this 12 months, Intel was a member of the Commonplace for Interfaces, Processors, and Techniques (CHIPS) Alliance, hosted by way of the Linux Basis, to give a contribution the AIB license as an open-source usual. The theory, in fact, was once to inspire trade adoption and facilitate a library of AIB-equipped chiplets.

“We lately have 10 AIB-based tiles from a couple of distributors which are both in-production or on power-on,” says Intel’s Nagisetty. “There are 10 extra tiles within the near-term horizon from ecosystem companions together with startups and college analysis teams.”

Foveros will increase density in a 3rd size

Breaking SoCs into reusable IP blocks and integrating them horizontally with high-density bridges is likely one of the tactics Intel plans to leverage production efficiencies and proceed scaling functionality. Your next step up, in step with the corporate’s packaging era roadmap, comes to stacking dies on most sensible of one another, face-to-face, the usage of fine-pitched micro-bumps. This three-d way, which Intel calls Foveros, closes the gap between dies, the usage of much less chronic to transport knowledge round. While Intel’s EMIB era is rated at kind of zero.50 pJ/bit, Foveros will get that all the way down to zero.15 pJ/bit.

Lakefield, the first product based on Foveros 3D die stacking, comprises a base die (22FFL) under a compute die (10nm), all of which is topped by package-on-package memory.

Above: Lakefield, the primary product according to Foveros three-D die stacking, contains a base die (22FFL) beneath a compute die (10nm), all of which is crowned by way of package-on-package reminiscence.

Like EMIB, Foveros lets in Intel to select the most efficient procedure era for every layer of its stack. The primary implementation of Foveros, code-named Lakefield, crams processing cores, reminiscence regulate, and graphics right into a die manufactured at 10nm. That chiplet sits on most sensible of the bottom die, which contains the purposes you’d generally in finding in a platform controller hub (audio, garage, PCIe, and so forth.), manufactured on a 14nm low-power procedure. Micro-bumps between the 2 pipe in chronic and communications via TSVs within the base die. Intel then tops the stack with LPDDR4X reminiscence from one in every of its companions.

An entire Lakefield equipment measures simply 12x12x1mm, enabling a brand new magnificence of gadgets between laptops and smartphones. However we don’t be expecting Foveros to just serve low-power programs. In a 2019 HotChips Q&A consultation, Intel fellow Wilfred Gomes predicted the era’s long term ubiquity. “…the best way we designed Foveros, we expect it’ll span all of the vary of the computing spectrum, from the lowest-end gadgets to the highest-end gadgets,” he mentioned.

Scalability offers us any other variable to believe

The packaging roadmap set forth all through Intel’s Structure Day 2020 plotted every era by way of interconnect density (the selection of microbumps in step with sq. millimeter) and gear potency (pJ of power expended in step with bit of knowledge transferred). Past Foveros, Intel is pursing die-on-wafer hybrid bonding to push each metrics even additional. It expects to succeed in greater than 10,000 bumps/mm² and no more than zero.05 pJ/bit.

Blending 2.5D and 3D packaging technologies yields Co-EMIB, which enables larger-than-reticle sized base dies plus Foveros die stacks on the same package.

Above: Mixing 2.5D and three-D packaging applied sciences yields Co-EMIB, which allows larger-than-reticle sized base dies plus Foveros die stacks at the similar equipment.

However complicated packaging applied sciences can be offering software past upper bandwidth and decrease chronic. A mix of EMIB and Foveros — dubbed Co-EMIB — guarantees scaling alternatives past both way by itself. There are not any real-world examples of Co-EMIB but. On the other hand, you’ll consider huge natural applications with embedded bridges connecting Fovoros stacks that mix accelerators and reminiscence for high-performance computing.

Intel’s Omni-Directional Interface (ODI) provides much more flexibility by way of linking chiplets subsequent to one another, connecting chiplets stacked vertically, and offering chronic to the highest die in a stack immediately via copper pillars. The ones pillars are bigger than the TSVs that run during the base die in a Foveros stack, minimizing resistance and making improvements to chronic supply. The liberty to glue dies in any path and stack bigger tiles on most sensible of smaller ones offers Intel much-needed flexibility in structure. It for sure looks as if a promising era for development on Foveros’ features.

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