UltraSoC launches "any processor" lockstep solution for safety-critical systems

CAMBRIDGE, UK – 29 November 2018 – UltraSoC, the chief in embedded analytics for the security and safety of automobile methods, lately introduced the UltraSoC Lockstep Observe. A hardware-based, scalable answer, the brand new Lockstep Observe considerably is helping purposeful security by means of checking that the cores on the center of a serious gadget are working reliably, safely and securely. UltraSoC’s versatile IP helps all not unusual lockstep / redundancy architectures, together with complete dual-redundant lockstep, cut up/lock, grasp/checker, and balloting with any selection of cores or subsystems.

The UltraSoC Lockstep Observe can strengthen any processor structure or different subsystem, together with customized common sense or accelerators. Lockstep operation is wanted for security requirements reminiscent of ISO26262 for automobile, IEC 61508, EN50126/eight/nine and CE 402/2013.

The brand new Lockstep Observe is composed of a collection of configurable semiconductor IP (SIP) blocks which are protocol mindful and can be utilized to cross-check outputs, bus transactions, code execution or even sign up states, between two or extra redundant methods. It may be used with any processor structure, together with the ones – such because the rising RISC-V structure – which lack local strengthen for lockstep configurations. Along with conventional processor cores, it might additionally test different subsystems or accelerators. As a result of it’s applied in , it responds at cord velocity and imposes no execution overhead at the host gadget.

In contrast to conventional approaches, the UltraSoC Lockstep Observe comprises versatile, run-time configurable embedded intelligence, permitting the SoC fashion designer to tailor the tracking and reaction gadget exactly to the applying. Tracking will also be applied at quite a lot of ranges of granularity: on the subsystem point (evaluating the outputs of the 2 processors); on the transaction point (as an example evaluating bus site visitors); on the instruction point, the usage of UltraSoC’s complex instruction hint capacity; and on the maximum elementary hardware-level, checking processor inner states or sign up contents.

By means of embedding intelligence within the gadget, UltraSoC additionally permits extra refined comparisons between the operation of the lockstep processors than will also be accomplished with conventional answers. As an example, if the lockstep processors percentage a reminiscence area, they can not function in highest, cycle-by-cycle synchronization. UltraSoC’s on-chip analytics can be utilized to correlate task throughout the redundant processors, and to tailor the reaction of the gadget relying at the nature of any detected anomalies.

RISC-V is gaining expanding traction in safety-critical packages, specifically within the automobile business. Then again, the RISC-V ecosystem as an entire lately lacks strengthen for the purposeful security and safety rules – reminiscent of lockstep operation – mandated by means of world requirements reminiscent of ISO26262 for purposeful security, J3061 for cybersecurity, IEC 61508, EN50126/eight/nine and CE 402/2013. UltraSoC’s Lockstep Observe permits any RISC-V gadget, whether or not the usage of open supply or industrial cores, to include refined security functions. The corporate will probably be presenting on automobile security and safety – collectively with Resiltech, the experts in resilient computing for serious methods –on the upcoming RISC-V Summit (Santa Clara, three – 6 Dec 2018).

Lockstep methods make use of two or extra processor subsystems operating the similar code in a redundant backup configuration. The cores is also clock-cycle synchronized, or offset by means of a small selection of cycles, an association that protects in opposition to temporary mistakes within the surrounding gadget. The outputs, code execution or bus site visitors from the subsystems are when compared and if the consequences range, an error will also be signaled. Lockstep methods with two processors are generally configured in a ‘grasp/checker’ association; the ones with greater than two processors might use ‘balloting’ or different redundancy schemes. Extra refined “cut up/lock” processor preparations might permit the lockstep serve as to be dynamically engaged and disengaged, permitting the cores to run in redundant mode or to run other code for upper efficiency.

Touch us to request the UltraSoC Lockstep Gadget product transient. UltraSoC’s not too long ago up to date white paper on ISO26262 is to be had as a loose obtain from the UltraSoC web page: The Case for embedded analytics in ISO26262 and automobile.

About UltraSoC
UltraSoC is a pioneering developer of analytics and tracking era on the center of the systems-on-chip (SoCs) that energy lately’s digital merchandise. The corporate’s embedded analytics era permits product designers so as to add complex cybersecurity, purposeful security and function tuning options; and it is helping get to the bottom of serious problems reminiscent of expanding gadget complexity and ever-decreasing time-to-market. UltraSoC’s era is delivered as semiconductor IP and device to shoppers within the client electronics, computing and communications industries. For more info seek advice from www.ultrasoc.com

Andy Gothard
+44 7768 082 zero44

David Marsden
+44 7968 407 739

Twitter: @ultrasoc


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